Estudio de paralelización de convertidores Flyback en aplicaciones de carga de baterías y condensadores de hasta 1.2 kilovatios

  1. Rodríguez Calvo, Carlos
Supervised by:
  1. Carlos López Díaz Director

Defence university: Universidad de León

Fecha de defensa: 14 April 2023

  1. José Luis Calvo Rolle Chair
  2. José Guillermo Rosas Mayoral Secretary
  3. Daniel Moríñigo Sotelo Committee member

Type: Thesis

Teseo: 803933 DIALNET


This PhD. Thesis describes the design of a control architecture for a Flyback controller for a power range up to 1.2 Kilowatts. The main potential application of this proposal is in battery charging systems. The battery charging system have to get adapted to multiple voltage ranges due to that the batteries are formed by different cells connected to reach the desired current and voltage outputs. The connection of different cells in parallel or series generates voltage drifts between cells. For this reason the battery packs have integrated battery balancing systems. The battery balancing must able to operate in wide voltage ranges depending on the number of cell managed by it. The functional feature makes necessary the integration of complex and expensive hardware elements. This PhD thesis proposes a novel architectural solution which minimizes the integration of passive components and improves its adaptability. The research procedure of this PhD and its methodology details the full conceptualisation and analysis process for this architecture. Each of its phases have been designed and verified with software tolls and specialized instrumentation, as oscilloscopes, signal generators, hardware elements and high power supplies. During the process of this PhD research have been stablished four key objectives and four secondary ones. These objectives have allowed defining and understanding the different technological aspects of the proposed architecture as they are: - The functional behaviour of the proposed architecture based on digital interruptions. The digital interruptions have latencies which can impact in the final behaviour. This study proposes different techniques to minimize their technological weaknesses. - Hardware architecture of buses and peripherals. The selection of peripherals and its internal distribution is specifically studied with the objective of maximizing the hardware resources to be able to create a real time adaptable system. - The synchronization of different cores: the proposed architecture is formed by two central processing units. The objectives of this research block were oriented in the study of the synchronization of both central processing units to maximize the hardware resources. - The synchronization of different controllers: The synchronization of different controllers allows increasing the current ranges and improving the integration of this architecture in multiple charging environments. Each o this objectives have been experimentally investigated, with a deep description of the procedure selected and the results of each research topic. These experimental results have been generated by using and specific evaluation board designed for the purpose of the PhD.